? semiconductor components industries, llc, 2011 october, 2011 ? rev. 1 1 publication order number: NTD5414N/d NTD5414N, nvd5414n power mosfet 24 amps, 60 volts single n ? channel dpak features ? low r ds(on) ? high current capability ? avalanche energy specified ? aec q101 qualified ? nvd5414n ? these devices are pb ? free and are rohs compliant applications ? led lighting and led backlight drivers ? dc ? dc converters ? dc motor drivers ? power supplies secondary side synchronous rectification maximum ratings (t j = 25 c unless otherwise specified) parameter symbol value unit drain ? to ? source voltage v dss 60 v gate ? to ? source voltage ? continuous v gs 20 v gate ? to ? source voltage ? nonrepetitive (t p < 10 s) v gs 30 v continuous drain current r jc (note 1) steady state t c = 25 c i d 24 a t c = 100 c 16 power dissipation r jc (note 1) steady state t c = 25 c p d 55 w pulsed drain current t p = 10 s i dm 75 a operating and storage temperature range t j , t stg ? 55 to +175 c source current (body diode) i s 24 a single pulse drain ? to ? source avalanche energy ? starting t j = 25 c (v dd = 50 v dc , v gs = 10 v, i l(pk) = 24 a, l = 0.3 mh, r g = 25 ) e as 86.4 mj lead temperature for soldering purposes, 1/8 from case for 10 seconds t l 260 c thermal resistance ratings parameter symbol max unit junction ? to ? case (drain) steady state (note 1) r jc 2.7 c/w r ja 58.6 stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. surface mounted on fr4 board using 1 sq in pad size, (cu area 1.127 sq in [1 oz] including traces). http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. ordering information v (br)dss r ds(on) max i d max (note 1) 60 v 24 a n ? channel d s g 5414n = device code y = year ww = work week g = pb ? free device 1 gate 3 source 2 drain 4 drain dpak case 369aa style 2 marking diagrams 1 2 3 4 yww 5414n 37 m @ 10 v
NTD5414N, nvd5414n http://onsemi.com 2 electrical characteristics (t j = 25 c unless otherwise specified) characteristics symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v ds = 0 v, i d = 250 a 60 v drain ? to ? source breakdown voltage temper- ature coefficient v (br)dss /t j 67.3 mv/ c zero gate voltage drain current i dss v gs = 0 v v ds = 60 v t j = 25 c 1.0 a t j = 150 c 50 gate ? body leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 2) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 2.0 3.2 4.0 v negative threshold temperature coefficient v gs(th) /t j 0.74 mv/ c drain ? to ? source on ? voltage v ds(on) v gs = 10 v, i d = 24 a 0.7 1.16 v v gs = 10 v, i d = 12 a, 150 c 0.7 drain ? to ? source on ? resistance r ds(on) v gs = 10 v, i d = 24 a 28.4 37 m forward transconductance g fs v ds = 15 v, i d = 20 a 24 s charges, capacitances & gate resistance input capacitance c iss v ds = 25 v, v gs = 0 v, f = 1 mhz 800 1200 pf output capacitance c oss 165 transfer capacitance c rss 75 total gate charge q g(tot) v gs = 10 v, v ds = 48 v, i d = 24 a 25 48 nc threshold gate charge q g(th) 1.1 gate ? to ? source charge q gs 4.8 gate ? to ? drain charge q gd 11.3 switching characteristics, v gs = 10 v (note 3) turn ? on delay time t d(on) v gs = 10 v, v dd = 48 v, i d = 24 a, r g = 9.1 12 ns rise time t r 58 turn ? off delay time t d(off) 47 fall time t f 69 drain ? source diode characteristics forward diode voltage (note 2) v sd v gs = 0 v i s = 24 a t j = 25 c 0.92 1.15 v t j = 125 c 0.8 reverse recovery time t rr i s = 24 a dc , v gs = 0 v dc , di s /dt = 100 a/ s 45.7 ns charge time t a 31.7 discharge time t b 14 reverse recovery stored charge q rr 76 nc 2. pulse test: pulse width 300 s, duty cycle 2%. 3. switching characteristics are independent of operating junction temperatures. ordering information device package shipping ? NTD5414Nt4g dpak (pb ? free) 2500 / tape & reel nvd5414nt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NTD5414N, nvd5414n http://onsemi.com 3 typical performance curves 0 10 20 30 40 35 012345 v ds , drain ? to ? source voltage (v) i d , drain current (a) figure 1. on ? region characteristics v gs = 4.2 v 4.5 v 6 v 10 v t j = 25 c 0 10 20 30 40 345 6 2 v gs , gate ? to ? source voltage (v) figure 2. transfer characteristics i d , drain current (a) t j = 25 c t j = ? 55 c t j = 125 c 0.02 0.03 0.04 0.05 0.06 0.07 0.08 567 8 910 v gs , gate ? to ? source voltage (v) r ds(on) , drain ? to ? source resistance ( ) figure 3. on ? resistance vs. gate ? to ? source voltage i d = 24 a t j = 25 c 0.010 0.020 0.030 10 20 30 40 15 45 i d , drain current (a) r ds(on) , drain ? to ? source resistance ( ) figure 4. on ? resistance vs. drain current and gate voltage t j = 25 c v gs = 10 v 0.5 1.0 1.5 2.0 2.5 ? 50 ? 25 0 25 50 75 100 125 150 175 t j , junction temperature ( c) r ds(on) , drain ? to ? source resistance (normalized) figure 5. on ? resistance variation with temperature i d = 24 a v gs = 10 v 10 100 1000 5 1015202530354045505560 v ds , drain ? to ? source voltage (volts) i dss , leakage (na) figure 6. drain ? to ? source leakage current vs. voltage v gs = 0 v t j = 150 c t j = 125 c v ds 10 v 0.040 5 15 25 7 v 4.8 v 5 v 5 15 25 35 25 35 5.5 v
NTD5414N, nvd5414n http://onsemi.com 4 typical performance curves 0 500 1000 1500 0 102030405060 v ds , drain ? to ? source voltage (v) figure 7. capacitance variation c, capacitance (pf) v gs = 0 v c rss c oss c iss t j = 25 c 1 10 100 1000 1 10 100 0 2 4 6 8 10 0 5 10 15 20 25 q g , total gate charge (nc) v gs , gate ? to ? source voltage (v) figure 8. gate ? to ? source voltage vs. total charge i d = 24 a t j = 25 c q t q 2 q 1 t, time (ns) r g , gate resistance ( ) figure 9. resistive switching time variation vs. gate resistance t r t f t d(off) t d(on) 0 5 10 15 20 0.4 0.5 0.6 0.7 0.8 0.9 1.0 v sd , source ? to ? drain voltage (v) i s , source current (a) figure 10. diode forward voltage vs. current v gs = 0 v t j = 25 c figure 11. maximum rated forward biased safe operating area 0 10 20 30 40 60 25 50 75 100 125 150 175 t j , starting junction temperature ( c) avalanche energy (mj) figure 12. maximum avalanche energy vs. starting junction temperature i d = 24 a v dd = 48 v i d = 24 a v gs = 10 v 25 50 70 90 80 v ds , drain ? to ? source voltage (v) i d , drain current (a) 0.1 10 100 1000 0.1 10 100 10 s 100 s 1 ms 10 ms dc 0 v v gs 10 v single pulse t c = 25 c r ds(on) limit thermal limit package limit 1 1
NTD5414N, nvd5414n http://onsemi.com 5 typical performance curves 0.001 0.01 0.1 1 10 100 0.000001 0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000 t, pulse time (s) figure 13. thermal response r(t), ( c/w) d = 0.5 0.2 0.1 0.05 0.02 0.01 surface ? mounted on fr4 board using 1 sq in pad size, 1 oz cu single pulse
NTD5414N, nvd5414n http://onsemi.com 6 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 NTD5414N/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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